Various types of semiconductor devices may be best fabricated using one or more layers of substantially crystalline semiconductor material. For example, the highest efficiency photovoltaic solar cells presently known are III-V multi-junction cells epitaxially grown on single crystal Ge or GaAs substrates. One significant obstacle to the widespread deployment of high efficiency, large surface area, semiconductor devices such as crystalline III-V multi-junction photovoltaic cells is extremely high cost. In particular, the cost of suitable quantities of single-crystal GaAs or Ge substrate can be prohibitive if the cells are prepared in quantity using known techniques.
In addition to high cost, known techniques for the preparation of certain crystalline semiconductor materials allows for substantial defects which may compromise device performance. For example, there presently exists a major problem with light emitting devices such as light emitting diodes (LEDs) and lasers for solid state lighting applications based upon InGaN alloys in crystalline form. In particular, the efficiency of known InGaN devices at wavelengths between approximately 500 nm and 600 nm, corresponding to what is known as the “green gap”, is very low. One possible cause of this efficiency problem is that the material quality of InGaN alloys having a suitable bandgap for emission in this wavelength region is degraded due to a tendency toward phase separation of the InGaN prepared by conventional techniques. One possibility for avoiding this serious problem is the epitaxial growth of lattice-matched InGaN alloys in which phase separation can be suppressed. Unfortunately, no suitable lattice-matched substrates for the epitaxial growth of InGaN alloys having band gaps suitable for emission in the “green gap” are known.
Because the cost of a single crystal substrate is prohibitive for large surface area devices such as thin film solar cells, most known thin-film cells are based on polycrystalline or amorphous device layers. The inclusion of polycrystalline layers may limit device performance. To overcome inefficiencies associated with polycrystalline layers, it is known in the prior art to fabricate large area, substantially crystalline, semiconductor devices beginning with a relatively inexpensive metallic substrate which has been processed to have a crystalline textured surface. The fabrication of these devices typically requires several intermediate fabrication steps and several buffer layers between the semiconductor alloy layer of interest, and the substrate. For example, a III-V semiconductor layer as is used for high efficiency solar cells will not typically lattice match with the crystalline structure of an inexpensive metal foil substrate. Accordingly, known techniques for preparing a large surface area semiconductor device on an inexpensive metal or metal alloy crystalline substrate involves the use of one or several buffer layers between the substrate and the semiconductor layer.
In particular, multiple buffer layers may be grown between the substrate and active layer to provide both a chemical barrier and a structural template upon which to grow the active semiconductor layer(s). A chemical barrier may be needed to prevent diffusion of potentially contaminating elements from the metal or metal alloy substrate into the semiconductor layer(s). A structural template is needed to properly lattice match the final buffer layer to the active semiconductor layer to minimize the density of defects in the active semiconductor layer(s).
The need to carefully lattice match between the crystalline substrate and the active semiconductor layer may require a large number of buffer layers which are carefully graded to transition from the substrate lattice parameter to the lattice parameter of the active layer. This technique for obtaining an approximate lattice match between each sequentially applied layer is known as a “graded buffer layer” approach. With a graded buffer layer approach, the number of buffer layers that must to be grown depends upon both the extent of lattice mismatch between the final active semiconductor layer and the substrate, and the extent of intermediate lattice mismatch which can be accepted.
The use of one or more buffer layers between the substrate and active semiconductor layer(s) introduces a different set of problems. Additional processing steps increases device cost. Furthermore, the buffer layers themselves may introduce impurities, defects or strain issues which negatively affect device performance.
The embodiments disclosed herein are intended to overcome one or more of the limitations described above. The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.